1. Field of the Invention
The present invention relates generally to non-volatile memory integrated circuits, and in particular to hole annealing of nitride storage memory cells that affect the threshold voltage of erased nitride storage memory cells.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a non-volatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.
A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names Nitride Read-Only Memory (NROM), SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
NROM devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of an NROM flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target threshold Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious when the technology keeps scaling down.
A typical flash memory cell structure positions a tunnel oxide layer between a conducting polysilicon tunnel oxide layer and a crystalline silicon semiconductor substrate. The substrate refers to a source region and a drain region separated by an underlying channel region. A flash memory read can be executed by a drain sensing or a source sensing. For source side sensing, one or more source lines are coupled to source regions of memory cells for reading current from a particular memory cell in a memory array.
A traditional floating gate device stores 1 bit of charge in a conductive floating gate. The advent of NROM cells in which each NROM cell provides 2 bits of flash cells that store charge in an Oxide-Nitride-Oxide (ONO) dielectric. In a typical structure of a NROM memory cell, a nitride layer is used as a trapping material located between a top oxide layer and a bottom oxide layer. The ONO layer structure effectively replaces the gate dielectric in a floating gate device.
A nitride storage memory cell such as an NROM cell has increasingly become more promising, especially a nitride memory cell with channel hot electron program and junction edge band-to-band hot hole erasure that combines with a reverse read. The nitride storage memory cell is able to provide two physical bits per cell, which enhances the overall memory capacity. After several program and erase cycles, however, the threshold voltage Vt after erase tends to draft undesirably higher after a period of waiting time. The drifting of the threshold voltage Vt may lead to a reduction in the margin of logical read 1 or erase bits.
Therefore, there is a need for a hole annealing method that monitors and adjusts the threshold voltage Vt after erase to reduce the amount of drifting in the threshold voltage.